Setup/Hold Time Margins - Defination with Design Problem

Setup Time (Tsu): Minimum time for which Input signal must be stable before the active edge of clock signal.
Negative Setup Time (-Tsu): Time for which the Input signal can change even after the active clock edge and in spite of this, the new level will be correctly recognised.

• This can be produced by internal delay of the clock signal.

Hold Time (Thold): Minimum Time for which Input signal must remain stable after the active edge of clock signal.
Negative Hold Time (-Thold): Time for which the input signal can change even before the clock edge and in spite of this, the old level will be correctly recognised.

• This can be produced by internal delay of the Input (data/control) signal.

Design Problem: Specification for a given design are

1. Tsu = -20 ps (Negative setup time)
2. Thold = +30 ps (Positive hold time)
3. Simulation starts @ 0 ps (Active edge)

Find out when the design will fail on a data transition?

Solution:

• From (1.) & (3.) 0 ps - 20 ps => Data transition can occur.
• From (1.) 20 ps + => Data transition will cause failure.
• From (2.) & (3.) 0 ps - 30 ps => Data transition will cause failure.
• From (2.) 30 ps + => Data transition can occur.

From the above four points: 20 ps - 30 ps => Data transition is not permitted as it can cause design failure.